The present invention relates to a semiconductor device, and particularly, to a technique for reducing ON resistance and increasing withstand voltage of a semiconductor device.
A related art as a background of the present invention is a standard MOSFET made of silicon carbide disclosed in, for example, Japanese Laid-Open Patent Publication No. Hei-10-233503 (Patent Reference 1).
FIG. 20 is a sectional view schematically showing the semiconductor device described in the Patent Reference 1. In FIG. 20, the semiconductor device has an n+-type silicon carbide substrate region 51 and an n−-type drain region 52 formed on the substrate region 51. At a part of the surface of the drain region 52, there are formed a p-type well region 53 and an n+-type source region 54. On the drain region 52, there are arranged an insulating film 55 and a gate electrode 56. In contact with the well region 53 and source region 54, a source electrode 57 is formed. On a back face of the silicon carbide substrate region 51, a drain electrode 58 is formed.
Operation of the MOSFET will be explained. For example, the source electrode 57 is grounded, the drain electrode 58 is subjected to a positive potential, and the gate electrode 56 is grounded or is subjected to a negative potential. Then, the drain region 52 and well region 53 become a reversely biased state to put the semiconductor device in a nonconductive state.
When a proper positive potential is applied to the gate electrode 56, an inversion channel region is formed at an interface of the well region 53 adjacent to the gate electrode 56 through the insulating film 55. Then, electrons flow from the source region 54 to the drain region 52 through the channel region. In this way, the related art realizes a switching function.